unable to create a ROM with datawidth more than 64

[anupkini]

I am unable to create a ROM with DATAWIDTH greater than 64.

Sample Code with testbench: import Chisel._

class DUT extends Module { val DATAWIDTH = 72

def matchLookUpRows() = { val inits = (1 to 2).map( i => UInt(i, width=DATAWIDTH)) ROM(inits) }

val io = new Bundle { val m = UInt(INPUT, width=log2Up(DATAWIDTH)) val fState = Bits(OUTPUT, width=DATAWIDTH) }

val inpBitStrReg = RegInit(Bits(0,width=DATAWIDTH))

inpBitStrReg := matchLookUpRows.read(io.m) io.fState := inpBitStrReg }

class DUTTester(c:DUT) extends Tester(c) { poke(c.io.m, 0) peek(c.inpBitStrReg) step(1) peek(c.inpBitStrReg) }

Error Message: cppBackend/DUT.cpp: In member function ‘virtual void DUT_t::init(val_t)’: cppBackend/DUT.cpp:7:18: error: ‘T5’ was not declared in this scope { T2.put(0, 0, T5[0]); T2.put(0, 1, T5[1]);} ^ cppBackend/DUT.cpp:8:18: error: ‘T6’ was not declared in this scope { T2.put(1, 0, T6[0]); T2.put(1, 1, T6[1]);} ^ [info] [0.623] g++ -c -o cppBackend/DUT.o -I../ -I/csrc/ -O0 cppBackend/DUT.cpp RET 1

[ucbjrl]

Fixed by #741 - incorporated in release 2.2.37, 23-Feb-2017.