genenarate top.v fail

[Kt985]

I keep getting the following error when I run the command that generates top.v.myfirtool is 1.4.5.

[info] running (fork) barstools.tapeout.transforms.GenerateModelStageMain --no-dedup --output-file /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc --output-annotation-file /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc.anno.json --target-dir /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral --input-file /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.fir --annotation-file /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.appended.anno.json --log-level error --allow-unrecognized-annotations -X none [error] Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=/1/chipyard/.java_tmp [success] Total time: 3 s, completed Jul 13, 2023 8:15:06 PM mv /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc.lo.fir /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc.fir 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL /1/chipyard/common.mk:196: recipe for target '/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/model_module_hierarchy.json' failed make: [/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/model_module_hierarchy.json] Error 1 (ignored) firtool \ --format=fir \ --dedup \ --export-module-hierarchy \ --emit-metadata \ --verify-each=true \ --warn-on-unprocessed-annotations \ --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --repl-seq-mem \ --repl-seq-mem-file=/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.mems.conf \ --repl-seq-mem-circuit=TestHarness \ --annotation-file=/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc.anno.json \ --split-verilog \ -o /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral \ /1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.TestHarness.TestConfig00.sfc.fir firtool: Unknown command line argument '--emit-metadata'. Try: 'firtool --help' firtool: Did you mean '--emit-bytecode'? firtool: Unknown command line argument '--repl-seq-mem-circuit=TestHarness'. Try: 'firtool --help' firtool: Did you mean '--repl-seq-mem-file=TestHarness'? /1/chipyard/common.mk:196: recipe for target '/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/model_module_hierarchy.json' failed make: *** [/1/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/model_module_hierarchy.json] Error 1

[Kt985]

update conda to the latest version and rebulid riscv toolchain can solve this problem