RISCV: Implement CSRR and CSRW

ucb-bar / esp-llvm

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

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RISCV: Implement CSRR and CSRW #14

Closed toad closed 9 years ago

toad commented 9 years ago

Note that this still doesn't make exception handling work because 1) the CSR names are out of date and 2) userspace exception handling isn't really supported upstream yet. But it's a step forward and I need it to set CSRs for tagged registers. Also, there are user-mode CSRs, notably cycle counters, so we will need this eventually.

ghost commented 9 years ago

Can one of the admins verify this patch?

toad commented 9 years ago

Please do NOT merge this. It does very odd things, inserting code like "CSRR x5, x5" while apparently trying to sign-extend a 64-bit ordinary register into another 64-bit ordinary register.

toad commented 9 years ago

The only reason I tried to implement this was I need to set some CSRs in the setup code for tagged memory. After more than a day I was completely unable to specify a specific physical register for an instruction in matching, and adding it as a custom lowering looked problematic too. I currently have a really gross hack, hardcoding the register number... Hopefully this won't be necessary in the long run because the loader or the kernel will set the CSRs...

colinschmidt commented 9 years ago

I actually had a similar problem recently with trying to get a specific physical register selected for an instruction. I ended up solving it by adding a pseudo instruction that has a custom emit fucntion. See 435cab1530b95c75a8c9088f2440bd8df0c18449