How to configure Gemmini/Chipyard to use verilog accelerator mesh?

[MrJbriggs]

Background: trying to replicate Lab 2 of EE290

I ran

make CONFIG=GemminiRocketConfig

to build a simulator for Gemmini but I do not see anything that tells me my verilog mesh is correctly linked or not.

I have the verilog located in vsrc like this:

generators/yourproject/ build.sbt src/main/ scala/ resources/ vsrc/ YourFile.v

But what else is needed? What does this instruction in section 6.10.1 of Chipyard doc mean?:

lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
  .dependsOn(chisel_testers, example, yourproject)
  .settings(commonSettings)

[MrJbriggs]

Getting some traction with this:

https://www.chisel-lang.org/chisel3/docs/explanations/blackboxes.html#:~:text=Chisel%20BlackBoxes%20are%20used%20to,IP%20not%20defined%20in%20Chisel.

And this

https://inst.eecs.berkeley.edu/~cs250/sp16/disc/Blackboxing.pdf

[hngenc]

You can use the ee290-sp21-lab2 branch for an example of how to incorporate Verilog into your design

[MrJbriggs]

Got it. Thank you @hngenc

I really appreciate your help