ASAP7 tutorial: make buildfile CONFIG=TinyRocketConfig

[Leon924]

when I run command: make buildfile CONFIG=TinyRocketConfig. Errors below came out and terminate in the end

[error] INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x4 port count must match [error] INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x8 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW128x16 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW128x32 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW128x4 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW128x8 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW16x16 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW16x32 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW16x4 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW16x8 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x16 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x22 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x32 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x33 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x39 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x4 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW32x8 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW64x16 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW64x24 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW64x32 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW64x4 port count must match [error] INFO: unable to compile l2_tlb_ram_ext using SRAM2RW64x8 port count must match [success] Total time: 6 s, completed Mar 28, 2022, 9:47:37 PM make: *** No rule to make target '/home/lx/hwgen0327/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/EICG_wrapper.v', needed by '/home/lx/hwgen0327/chipyard/vlsi/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml'. Stop.

the generated-src fold has contain top.mems.v. but didn't output build folder. What should I do next?@harrisonliew

Thank you, Best regards, Leon.

[harrisonliew]

This is actually because barstools' MacroCompiler is too verbose and expects a certain order of 1-port and 2-port RAMs: https://github.com/ucb-bar/barstools/blob/master/src/main/scala/barstools/macros/MacroCompiler.scala#L640. As long as you have the generated top.mems.v file, MacroCompiler worked correctly and you can ignore these errors.

As for the Make error, it looks like for some reason, /home/lx/hwgen0327/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/EICG_wrapper.v doesn't exist? This should automatically be placed in that folder after elaborating your design. If it's not there, something in Chipyard may have changed so that it doesn't place it there, so in that case, can you try changing this line: https://github.com/ucb-bar/chipyard/blob/master/vlsi/Makefile#L59 to extra_v_includes = $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v and see if that works?

[Leon924]

1. Thanks for your explainations. so then I can ignore them.

2. EICG_wrapper.v exists in the output generated-src folder. It came out first when I run make command. But It still terminates when I try make clean; make buildfile again. And then I try make buildfile twice without clean. It works! But the output sram_generator-rundir is empty. Is it normal ? What it is used for?

3. by the way, I see MacroCompiler accept top.mems.conf as input. One line of this file writes: name data_arrays_0_0_ext depth 1024 width 32 ports mrw mask_gran 32 Can I thinks mrw as multiple read&write ports? mask_gran as mask granularity?

[harrisonliew]

The ASAP7 SRAM compiler doesn't use the sram_generator-rundir, so it is empty. Instead it puts a .lib file in the tech-asap7-cache just to track what it has compiled.

Yes, you are correct about the mems.conf stuff. The spec is here: https://github.com/ucb-bar/barstools/blob/master/src/main/scala/mdf/macrolib/ConfReader.scala

[Leon924]

Hi, Harrison:

my linux server version is Ubuntu18.04 and using VCS2017 to simulate default config. Due to the version of VCS is not so suitable for ubuntu18, I revise vcs.mk according to the workaround here. [https://github.com/chipsalliance/rocket-chip/issues/1377]

VCS_CC_OPTS = \ -CFLAGS "$(VCS_CXXFLAGS)" \ -LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ $(filter -l%,$(VCS_LDFLAGS)) \ -cpp g++-4.8 -cc gcc-4.8 \ -LDFLAGS -WI,--no-as-needed

I can use VCS to simulate other project wrote by myself. So VCS works well outsides hammer. Then I run comand make sim-rtl CONFIG=TinyRocketConfig, it output errors below.

/usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snps_mem_malloc_from_group' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tovfs::ftell(vfs::CFile)' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsCheckMallocFromGroupFunc' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnps_mem_group_set_thread_private' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsValloc' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnpsReallocFunc' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsReallocFromGroup' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tovfs_restore_native_fp' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsGetMemBytes' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnps_mem_set_exec_name' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to `vfs::vfsReleaseVirtualFileList(VFILE_LIST)'Action sim failed with errors

/usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to vfs_stat' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tovfs_dirstat_cache' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsNamedAllocateGroup' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsucli.so: undefined reference tovfs_get_sdb_native_file_descr' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to snpsLowMemory' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnpsCurrentGroup' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to vfs::CFile::access(char const*, char const*, int, vcsfs_t, unsigned int)' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnps_mem_set_trace_text' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to vfs_stdout' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnps_mem_get_group_name' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to ZsGetNumUscopes' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnpsOutOfMem' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to ZsGetDfsInstId' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference tosnps_mem_realloc' /usr/local/bin/ld: /home/liqiang/eda/app/synopsys/vcs/N-2017.12-1/linux64/lib/libvcsnew.so: undefined reference to `snps_mem_named_push_context' collect2: error: ld returned 1 exit status Makefile:106: recipe for target 'product_timestamp' failed make[1]: [product_timestamp] Error 1 make[1]: Leaving directory '/home/liqiang/socgen/hwgen0327/chipyard/vlsi/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/sim-rtl-rundir/csrc' Make exited with status 2 [] Simulation tool vcs failed! Please check its output. [] Nothing set for the paths to output waveforms yet [] Sim tool did not succeed make: [/home/liqiang/socgen/hwgen0327/chipyard/vlsi/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/sim-rtl-rundir/sim-output-full.json] Error 1 /home/liqiang/socgen/hwgen0327/chipyard/vlsi/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/hammer.d:44: recipe for target '/home/liqiang/socgen/hwgen0327/chipyard/vlsi/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/sim-rtl-rundir/sim-output-full.json' failed

What do I need to do to fix this problem? maybe I miss some settings? @harrisonliew

full-log is here: [hammer-sim-rtl.log](https://github.com/ucb-bar/hammer/files/8386982/hammer-sim-rtl.log)

Best, Leon

[harrisonliew]

It looks to me like you are trying to use the workaround to use gcc-4.8 but your dynamic linker/loader is still the default on in usr/local/bin/ld (what version is your glibc install? Resource to check here.). Different VCS versions are indeed sensitive to the C libraries/linkers versions you have installed and I believe your glibc needs to be no older than your gcc.

[Leon924]

Hi，harrison: I change another Environment : RHEL 6.10, VCS 2018, and enbale devtoolset-8 bash, so the gcc verison is 8.3.1. About glibc version: checking with ldd --versio, is glibc-2.12

First, I validate the VCS and system environment by running make and simulation in sim/vcs of MediumBoomConfig, it's running successfully. then, when I run the command in VLSI foder(make buildfile ahead): make sim-rtl CONFIG=MediumBoomConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple | tee -i MBoom-sim.log

g++ -w -pipe -fPIC -I/export/Apps/Synopsys/vcs/O-2018.09-SP2-2/include -std=c++11 -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/riscv-tools-install/include -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/tools/DRAMSim2 -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/generated-src/chipyard.TestHarness.MediumBoomConfig -std=c++11 -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/riscv-tools-install/include -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/tools/DRAMSim2 -I/export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/generated-src/chipyard.TestHarness.MediumBoomConfig -O3 -I/export/Apps/Synopsys/vcs/O-2018.09-SP2-2/include -c /export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/generated-src/chipyard.TestHarness.MediumBoomConfig/uart.cc cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C mm.o: In function mm_t::init(unsigned long, int, int)': mm.cc:(.text+0x0): multiple definition ofmm_t::init(unsigned long, int, int)' mm.o:mm.cc:(.text+0x0): first defined here mm.o: In function mm_t::write(unsigned long, unsigned char*, unsigned long, unsigned long)': mm.cc:(.text+0xa0): multiple definition ofmm_t::write(unsigned long, unsigned char, unsigned long, unsigned long)' mm.o:mm.cc:(.text+0xa0): first defined here mm.o: In function mm_t::read(unsigned long)': mm.cc:(.text+0x130): multiple definition ofmm_t::read(unsigned long)' mm.o:mm.cc:(.text+0x130): first defined here mm.o: In function mm_t::~mm_t()': mm.cc:(.text+0x320): multiple definition ofmm_t::~mm_t()' mm.o:mm.cc:(.text+0x320): first defined here mm.o: In function mm_t::~mm_t()': mm.cc:(.text+0x320): multiple definition ofmm_t::~mm_t()' mm.o:mm.cc:(.text+0x320): first defined here mm.o: In function mm_t::~mm_t()': mm.cc:(.text+0x340): multiple definition ofmm_t::~mm_t()' mm.o:mm.cc:(.text+0x340): first defined here mm.o: In function `mm_t::load_mem(unsigned long, char const)': mm.cc:(.text+0x360): multiple definition of mm_t::load_mem(unsigned long, char const*)' mm.o:mm.cc:(.text+0x360): first defined here mm.o: In functionmm_magic_t::init(unsigned long, int, int)': mm.cc:(.text+0x800): multiple definition of mm_magic_t::init(unsigned long, int, int)' mm.o:mm.cc:(.text+0x800): first defined here mm.o: In functionmm_magic_t::tick(bool, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, void, bool, bool, bool)': mm.cc:(.text+0x840): multiple definition of `mm_magic_t::tick(bool, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, void, bool, bool, bool)' mm.o:mm.cc:(.text+0x840): first defined here mm_dramsim2.o: In function power_callback(double, double, double, double)': mm_dramsim2.cc:(.text+0x0): multiple definition ofpower_callback(double, double, double, double)' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x0): first defined here mm_dramsim2.o: In function mm_dramsim2_t::ar_ready() [clone .localalias.194]': mm_dramsim2.cc:(.text+0x10): multiple definition ofmm_dramsim2_t::ar_ready()' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x10): first defined here mm_dramsim2.o: In function mm_dramsim2_t::aw_ready() [clone .localalias.193]': mm_dramsim2.cc:(.text+0x20): multiple definition ofmm_dramsim2_t::aw_ready()' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x20): first defined here mm_dramsim2.o: In function mm_dramsim2_t::read_complete(unsigned int, unsigned long, unsigned long)': mm_dramsim2.cc:(.text+0x40): multiple definition ofmm_dramsim2_t::read_complete(unsigned int, unsigned long, unsigned long)' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x40): first defined here mm_dramsim2.o: In function mm_dramsim2_t::write_complete(unsigned int, unsigned long, unsigned long)': mm_dramsim2.cc:(.text+0x6f0): multiple definition ofmm_dramsim2_t::write_complete(unsigned int, unsigned long, unsigned long)' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x6f0): first defined here mm_dramsim2.o: In function mm_dramsim2_t::tick(bool, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, void*, bool, bool, bool)': mm_dramsim2.cc:(.text+0x9d0): multiple definition ofmm_dramsim2_t::tick(bool, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, unsigned long, unsigned long, unsigned long, bool, unsigned long, void, bool, bool, bool)' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x9d0): first defined here mm_dramsim2.o: In function mm_dramsim2_t::init(unsigned long, int, int)': mm_dramsim2.cc:(.text+0x11f0): multiple definition ofmm_dramsim2_t::init(unsigned long, int, int)' mm_dramsim2.o:mm_dramsim2.cc:(.text+0x11f0): first defined here remote_bitbang.o: In function remote_bitbang_t::remote_bitbang_t(unsigned short)': remote_bitbang.cc:(.text+0x0): multiple definition ofremote_bitbang_t::remote_bitbang_t(unsigned short)' remote_bitbang.o:remote_bitbang.cc:(.text+0x0): first defined here remote_bitbang.o: In function remote_bitbang_t::remote_bitbang_t(unsigned short)': remote_bitbang.cc:(.text+0x0): multiple definition ofremote_bitbang_t::remote_bitbang_t(unsigned short)' remote_bitbang.o:remote_bitbang.cc:(.text+0x0): first defined here remote_bitbang.o: In function remote_bitbang_t::accept()': remote_bitbang.cc:(.text+0x200): multiple definition ofremote_bitbang_t::accept()' remote_bitbang.o:remote_bitbang.cc:(.text+0x200): first defined here remote_bitbang.o: In function remote_bitbang_t::reset()': remote_bitbang.cc:(.text+0x2b0): multiple definition ofremote_bitbang_t::reset()' remote_bitbang.o:remote_bitbang.cc:(.text+0x2b0): first defined here remote_bitbang.o: In function remote_bitbang_t::set_pins(char, char, char)': remote_bitbang.cc:(.text+0x2c0): multiple definition ofremote_bitbang_t::set_pins(char, char, char)' remote_bitbang.o:remote_bitbang.cc:(.text+0x2c0): first defined here remote_bitbang.o: In function remote_bitbang_t::execute_command()': remote_bitbang.cc:(.text+0x2d0): multiple definition ofremote_bitbang_t::execute_command()' remote_bitbang.o:remote_bitbang.cc:(.text+0x2d0): first defined here remote_bitbang.o: In function `remote_bitbang_t::tick(unsigned char, unsigned char, unsigned char, unsigned char, unsigned char)': remote_bitbang.cc:(.text+0x510): multiple definition of `remote_bitbang_t::tick(unsigned char, unsigned char, unsigned char, unsigned char, unsigned char)' remote_bitbang.o:remote_bitbang.cc:(.text+0x510): first defined here SimDRAM.o: In function memory_tick': SimDRAM.cc:(.text+0x0): multiple definition ofmemory_tick' SimDRAM.o:SimDRAM.cc:(.text+0x0): first defined here SimDRAM.o: In function memory_init': SimDRAM.cc:(.text+0x1b0): multiple definition ofmemory_init' SimDRAM.o:SimDRAM.cc:(.text+0x1b0): first defined here SimDRAM.o:(.data+0x0): multiple definition of dramsim' SimDRAM.o:(.data+0x0): first defined here SimDRAM.o:(.bss+0x8): multiple definition ofini_dir' SimDRAM.o:(.bss+0x8): first defined here SimDRAM.o:(.bss+0x0): multiple definition of loadmem_file' SimDRAM.o:(.bss+0x0): first defined here SimDRAM.o:(.bss+0x10): multiple definition ofloadmem_addr' SimDRAM.o:(.bss+0x10): first defined here SimJTAG.o: In function jtag_tick': SimJTAG.cc:(.text+0x0): multiple definition ofjtag_tick' SimJTAG.o:SimJTAG.cc:(.text+0x0): first defined here SimJTAG.o:(.bss+0x0): multiple definition of jtag' SimJTAG.o:(.bss+0x0): first defined here SimSerial.o: In functionserial_tick': SimSerial.cc:(.text+0x0): multiple definition of serial_tick' SimSerial.o:SimSerial.cc:(.text+0x0): first defined here SimSerial.o:(.bss+0x0): multiple definition oftsi' SimSerial.o:(.bss+0x0): first defined here SimUART.o: In function uart_init': SimUART.cc:(.text+0x0): multiple definition ofuart_init' SimUART.o:SimUART.cc:(.text+0x0): first defined here SimUART.o:(.bss+0x0): multiple definition of uart' SimUART.o:(.bss+0x0): first defined here SimUART.o: In functionuart_tick': SimUART.cc:(.text+0x80): multiple definition of uart_tick' SimUART.o:SimUART.cc:(.text+0x80): first defined here testchip_tsi.o: In functiontestchip_tsi_t::testchip_tsi_t(int, char, bool)': testchip_tsi.cc:(.text+0x0): multiple definition of `testchip_tsi_t::testchip_tsi_t(int, char, bool)' testchip_tsi.o:testchip_tsi.cc:(.text+0x0): first defined here testchip_tsi.o: In function testchip_tsi_t::testchip_tsi_t(int, char**, bool)': testchip_tsi.cc:(.text+0x0): multiple definition oftestchip_tsi_t::testchip_tsi_t(int, char**, bool)' testchip_tsi.o:testchip_tsi.cc:(.text+0x0): first defined here testchip_tsi.o: In function `testchip_tsi_t::write_chunk(unsigned long, unsigned long, void const) [clone .localalias.51]': testchip_tsi.cc:(.text+0x460): multiple definition of testchip_tsi_t::write_chunk(unsigned long, unsigned long, void const*)' testchip_tsi.o:testchip_tsi.cc:(.text+0x460): first defined here testchip_tsi.o: In functiontestchip_tsi_t::read_chunk(unsigned long, unsigned long, void)': testchip_tsi.cc:(.text+0x490): multiple definition of `testchip_tsi_t::read_chunk(unsigned long, unsigned long, void)' testchip_tsi.o:testchip_tsi.cc:(.text+0x490): first defined here testchip_tsi.o: In function testchip_tsi_t::reset()': testchip_tsi.cc:(.text+0x4c0): multiple definition oftestchip_tsi_t::reset()' testchip_tsi.o:testchip_tsi.cc:(.text+0x4c0): first defined here uart.o: In function sighand(int)': uart.cc:(.text+0x0): multiple definition ofsighand(int)' uart.o:uart.cc:(.text+0x0): first defined here uart.o:(.bss+0x0): multiple definition of specialchar' uart.o:(.bss+0x0): first defined here uart.o: In functionuart_t::~uart_t()': uart.cc:(.text+0x60): multiple definition of uart_t::~uart_t()' uart.o:uart.cc:(.text+0x60): first defined here uart.o: In functionuart_t::~uart_t()': uart.cc:(.text+0x60): multiple definition of uart_t::~uart_t()' uart.o:uart.cc:(.text+0x60): first defined here uart.o: In functionuart_t::tick(unsigned char, unsigned char, char, unsigned char, unsigned char, char)': uart.cc:(.text+0x80): multiple definition of `uart_t::tick(unsigned char, unsigned char, char, unsigned char, unsigned char, char)' uart.o:uart.cc:(.text+0x80): first defined here uart.o: In function uart_t::uart_t(char const*, int)': uart.cc:(.text+0x140): multiple definition ofuart_t::uart_t(char const, int)' uart.o:uart.cc:(.text+0x140): first defined here uart.o: In function `uart_t::uart_t(char const, int)': uart.cc:(.text+0x140): multiple definition of `uart_t::uart_t(char const*, int)' uart.o:uart.cc:(.text+0x140): first defined here collect2: error: ld returned 1 exit status Makefile:108: recipe for target 'product_timestamp' failed make[1]: *** [product_timestamp] Error 1 make[1]: Leaving directory '/export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/build/chipyard.TestHarness.MediumBoomConfig-ChipTop/sim-rtl-rundir/csrc' Make exited with status 2 [] Simulation tool vcs failed! Please check its output. [] Nothing set for the paths to output waveforms yet [] Sim tool did not succeed /export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/build/chipyard.TestHarness.MediumBoomConfig-ChipTop/hammer.d:44: recipe for target '/export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/build/chipyard.TestHarness.MediumBoomConfig-ChipTop/sim-rtl-rundir/sim-output-full.json' failed

MediumBoom-sim.log

The full log is above, How Can I fix this Multiple definition warning here?

[jerryz123]

Thanks for uploading the full log. Can you also upload the full log from compiling the simulator in sims/vcs?

[Leon924]

I finally fix this issue. I found out hammer-synopsys_plugin/sim/vcs plugin file：__init__.py maybe have some problem, cause the self.get_settting functions return a list which have duplicate elements, that leads many duplicated options in running vcs compilation (not simulte). I have some debug log below, full log has been deleted.

I was checking all options resulting in the error , so the log has been sorted out.

mediumboom-VCScompileOptions.log

line 15-18 , line 23 are duplicated, it come from options, abspath_input_files variables.

I dont know whether only me has this problem or not

[Leon924]

and according to https://github.com/ucb-bar/hammer/issues/642#issuecomment-1098708728 I try the new __init__.py updated by harrison. it has some probem with VCS 2018 in running simulation.

asap7-mb-sim-newinit.log

Error-[FGP_AFFINITY_FAILED] cpu_affinity/auto_affinity failed Failed to allocate CPU cores: Simulation threads requested 12 cores but only 0 core(s) are available. This machine has 40 physical cores. 40 core(s) are loaded with other jobs. For more details on status of CPU cores, please use runtime option -fgp=diag:ruse

then I try with simulation option -fgp=diag:ruse,num_threads:11,num_fsdb_threads:11,allow_less_cores it shows errors bleow: 7-mb-sim-newinit-diagruse.log I think cpu 40-79 are idle enough to load 11 threads? so what's problem with that?

[harrisonliew]

So the update to the Synopsys plugin was enabling VCS Fine-Grained Paralellism. This is supposed to work in VCS 2018, though based on the log it looks like it doesn't support hyper-threading (not in the documentation) and all of your cores are busy with other jobs.

From the documentation, you can try adding the single_socket_mode runtime option. According to the documentation, "All cores are treated as available irrespective of the current CPU load", so perhaps it won't error out. Or, just remove all -fgp in runtime to do a single-core simulation.

Also, about the duplicated options: did this go away when you updated the Synopsys plugin? We have not seen this before. If it still is a problem, can you attach the generated sim-inputs.yml file?

[Leon924]

1. I use the before-update __init__.py . Please checking log(a-mb-sim-ori.log) below, the options and the abspath_input_files variable (https://github.com/ucb-bar/hammer-synopsys-plugins/blob/696589f3fec890722539653a9b259dcc860c1f7d/sim/vcs/__init__.py#L134 https://github.com/ucb-bar/hammer-synopsys-plugins/blob/696589f3fec890722539653a9b259dcc860c1f7d/sim/vcs/__init__.py#L141 )have four duplilcated files(top.v top.mem.v harness.v harness.mem.v ). Unfortuntely , log didnt show ‘PASSED’ in the end and no saif outputs, but the finish time of simualation is exactly same as last time I succeed. Cause I tried to make sim-rtl using rv32ui-p-simple few days ago, It has PASSED message（see picture below） I don't know the reason why failed today. a -mb-sim-ori.log sim-inputs.txt

2. Also try using the updated __init__.py , at the same time , revise to single_socket_mode runtime option. But it's fatal in Icache . log and yml are here: Fatal: "/export1/Workspace/liqiang/socgen/hwgen/chipyard/vlsi/generated-src/chipyard.TestHarness.MediumBoomConfig/chipyard.TestHarness.MediumBoomConfig.top.v", 191091: TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache: at time 2865500000 fs a-mb-sim-new-ssm.log sim-inputs.txt

[harrisonliew]

The duplicated files actually comes from the Makefile: https://github.com/ucb-bar/chipyard/blob/main/vlsi/Makefile#L229-L232 and https://github.com/ucb-bar/chipyard/blob/main/vlsi/Makefile#L129-L131 and the `$(VCS_NONCC_OPTS). This isn't a problem for VCS - it will ignore previously defined modules.

Judging from your logs, this icache-caused fatal error seems similar to #642. Can you pull up some waveforms to see if there's an issue with an incorrect icache tag read/write? I'm thinking there's some bug in the VCS FGP or incompatibility with our generated binaries that is causing simulations to fail. If this is confirmed, then I will revert the Chipyard + Synopsys plugin PRs that enabled VCS FGP until we find a fix.

[Leon924]

I have these test cases below，why dhrystone can not pass in the original plugin? but succeed in sim/vcs mb-sim-dhry.log

under VLSI folder ： make sim-rtl-debug CONFIG=MediumBoomConfig BINARY=*

  | rv64ui-p-simple | rv32-p-simple | dhrystone -- | -- | -- | -- original * | PASS | PASS | Fatal [a-mb-simdebug-ori-dhry.log](https://github.com/ucb-bar/hammer/files/8501005/a-mb-simdebug-ori-dhry.log) updated* | Fatal | Fatal | Fatal [a-mb-simdebug-new-dhry.log](https://github.com/ucb-bar/hammer/files/8501001/a-mb-simdebug-new-dhry.log)

original *: before updated sim plugin,ie, no fgp

updated*: with fgp

[harrisonliew]

Right, fgp is not working, somehow, and we're still debugging in #642. Can you use the Synopsys plugin before the FGP update: (commit hash 81720fdd5b7fd747f34606f09b8a7d0da438a3ef) for now?

[Leon924]

Yes, for now this fgp feature is not necessary for debuging. But later, this feature would be exciting. However, in the before-updated case, why the dhrystone benchmark can not pass the test?

and another thing I wanna ask for help. because I need to make customed-config many times, how can I shorten the time of make stage, Maybe I need to revise JAVA_TOOL_OPTIONS: -Xmx16G -Xss8M by increasing Xmx?

[jerryz123]

Can you zip up and email me the various files of the dhrystone failure case for MediumBoom? Specifically, the waveform and the generated verilog for the design.

[Leon924]

sure ！ I have send the tarball to you. Edit： The letter always be rejected. please download here. https://drive.google.com/file/d/1sMI272igA_svb9Cro3XPBFoqRtZ9eF8t/view?usp=sharing

[Leon924]

fixed ！ close here