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ucb-bar / hwacha-template

Template for projects using the Hwacha data-parallel accelerator
http://hwacha.org/
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Synthesizable verilog #7

Open sdimascio opened 4 years ago

sdimascio commented 4 years ago

Is the verilog from "make verilog" in vsim supposed to be synthesizable like in other Rocket repositories? I can't find the top level for the synthesis. Also, are you planning to release a template design for an FPGA in the future?

a0u commented 4 years ago

Yes, the emitted Verilog is synthesizable in the same style as rocket-chip. When reading into a synthesis tool, the SYNTHESIS macro must be defined in order for non-synthesizable constructs to be properly excluded.

The design is contained in vsim/generated-src/*.top.v. Also needed are additional Verilog sources listed in vsim/generated-src/firrtl_black_box_resource_files.top.f.

vsim/generated-src/*.mems.v contains behavioral models for synchronous memories. The Xilinx FPGA tools should correctly infer these as BRAMs. For an ASIC, however, additional work is required to map them to technology-specific SRAM macros.

Currently, the best supported FPGA flow involves Chipyard (the successor to hwacha-template), which integrates Hwacha with FireSim to build and run AWS F1 images. Unfortunately, it is not possible to target local FPGA boards yet.