Hwacha Assertions

[palmer-dabbelt]

@jerryz123 is trying to port some BLAS-like stuff to Hwacha and he's found that it asserts when running any code. He's running HwachaConfig. By commenting out assertions he was able to get it to run the ASM tests.

diff --git a/src/main/scala/lane.scala b/src/main/scala/lane.scala
index 8014aef..b9e51a2 100644
--- a/src/main/scala/lane.scala
+++ b/src/main/scala/lane.scala
@@ -181,7 +181,7 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
     require(n <= uop.bits.nOperands)
     (0 until n) map { i =>
       val ri = rbase+i
-      assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)
+      // assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)
       Mux(uop.bits.sreg(i), splat_scalar(ctrl.io.uop.sreg(ri).bits), opls(ri))
     }
   }
@@ -208,9 +208,9 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
   io.lrqs(1).valid := ctrl.io.uop.vqu.valid && ctrl.io.uop.vqu.bits.fn.latch(1) && vqu_pred.active()
   io.lrqs(1).bits.data := vqu_operands(1)

-  assert(!io.lpqs(0).valid || io.lpqs(0).ready, "check lpqs(0) counter logic")
-  assert(!io.lrqs(0).valid || io.lrqs(0).ready, "check lrqs(0) counter logic")
-  assert(!io.lrqs(1).valid || io.lrqs(1).ready, "check lrqs(1) counter logic")
+  //assert(!io.lpqs(0).valid || io.lpqs(0).ready, "check lpqs(0) counter logic")
+  //assert(!io.lrqs(0).valid || io.lrqs(0).ready, "check lrqs(0) counter logic")
+  //assert(!io.lrqs(1).valid || io.lrqs(1).ready, "check lrqs(1) counter logic")

   val vgu_pred = predicate(3)
   val vgu_operands = operands("vgu", ctrl.io.uop.vgu, 1, 5)
@@ -219,8 +219,8 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
   io.lrqs(2).valid := ctrl.io.uop.vgu.valid && vgu_pred.active()
   io.lrqs(2).bits.data := vgu_operands(0)

-  assert(!io.lpqs(1).valid || io.lpqs(1).ready, "check lpqs(1) counter logic")
-  assert(!io.lrqs(2).valid || io.lrqs(2).ready, "check lrqs(2) counter logic")
+  //assert(!io.lpqs(1).valid || io.lpqs(1).ready, "check lpqs(1) counter logic")
+  //assert(!io.lrqs(2).valid || io.lrqs(2).ready, "check lrqs(2) counter logic")

   val vimu_pred = predicate(0)
   val vimu_operands = operands("vimu", ctrl.io.uop.vimu, 2, 0)

diff --git a/hwacha b/hwacha
--- a/hwacha
+++ b/hwacha
@@ -1 +1 @@
-Subproject commit 9367d958cd2a917e2b9f2d8dc893e4e8517fa7ac
+Subproject commit 9367d958cd2a917e2b9f2d8dc893e4e8517fa7ac-dirty
diff --git a/project/build.scala b/project/build.scala
index 8004792..0ee8f52 100644
--- a/project/build.scala
+++ b/project/build.scala
@@ -20,7 +20,7 @@ object BuildSettings extends Build {
   lazy val cde        = project in file("context-dependent-environments")
   lazy val hardfloat  = project.dependsOn(chisel)
   lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(chisel, cde, hardfloat)
-
+  lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings)
   lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
   lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
   val setMake = NotSpace ~ ( Space ~> NotSpace )
diff --git a/riscv-tools b/riscv-tools
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 1fca1bf57f227fa4e85cbdef0615873229d4d354
+Subproject commit 1fca1bf57f227fa4e85cbdef0615873229d4d354-dirty
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 90f4871..909bb59 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -131,6 +131,8 @@ class DualBankConfig extends Config(
   new WithNBanksPerMemChannel(2) ++ new BaseConfig)
 class DualBankL2Config extends Config(
   new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
+class QuadBankL2Config extends Config(
+  new WithNBanksPerMemChannel(4) ++ new WithL2Cache ++ new BaseConfig)

 class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
 class DualChannelL2Config extends Config(
diff --git a/src/main/scala/rocketchip/PrivateConfigs.scala b/src/main/scala/rocketchip/PrivateConfigs.scala
index 1c8a823..6e4b0cc 100644
--- a/src/main/scala/rocketchip/PrivateConfigs.scala
+++ b/src/main/scala/rocketchip/PrivateConfigs.scala
@@ -83,6 +83,25 @@ class ISCA2016Config extends Config(
   }
 }

+class ISCA2016Config1 extends Config(
+  new Process28nmConfig ++
+  new WithNMemoryChannels(1) ++ new WithNBanksPerMemChannel(4) ++
+  new WithNL2AcquireXacts(4) ++ new WithL2Capacity(256) ++ new With32BtbEntires ++ new HwachaConfig)
+{
+  override val knobValues:Any=>Any = {
+    case "HWACHA_NSRAMRF_ENTRIES" => 256
+    case "HWACHA_BUILD_VRU" => true
+    case x => (new Config(new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++ new WithL2Capacity(256) ++ new HwachaConfig)).knobValues(x)
+  }
+
+  override val topConstraints:List[ViewSym=>Ex[Boolean]] = {
+    List(
+      {ex => (ex(HwachaNSRAMRFEntries) === 256)},
+      {ex => (ex(HwachaBuildVRU) === true || ex(HwachaBuildVRU) === false)}
+    )
+  }
+}
+
 class ISCA2016L2Config extends Config(new WithNLanes(2) ++ new ISCA2016Config)
 class ISCA2016L4Config extends Config(new WithNLanes(4) ++ new ISCA2016Config)

diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala
index 26c60d9..5d44a04 100644
--- a/src/main/scala/uncore/tilelink2/Monitor.scala
+++ b/src/main/scala/uncore/tilelink2/Monitor.scala
@@ -35,7 +35,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
     when (bundle.opcode === TLMessages.Get) {
       assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
       assert (source_ok, "'A' channel Get carries invalid source ID" + extra)
-      assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
+      //assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
       assert (bundle.param === UInt(0), "'A' channel Get carries invalid param" + extra)
       assert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
     }
@@ -253,7 +253,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source

     when (bundle.opcode === TLMessages.AccessAckData) {
       assert (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
-      assert (is_aligned, "'D' channel AccessAckData address not aligned to size" + extra)
+      //assert (is_aligned, "'D' channel AccessAckData address not aligned to size" + extra)
       assert (sink_ok, "'D' channel AccessAckData carries invalid sink ID" + extra)
       // size is ignored
       assert (bundle.param === UInt(0), "'D' channel AccessAckData carries invalid param" + extra)

[colinschmidt]

Are they firing on the first cycle/during reset? Is this in the emulator or vsim?

[colinschmidt]

BTW I run HwachaConfig on the buildbot using vsim and it passes all its assembly tests and benchmarks.

[palmer-dabbelt]

@jerryz123 I'm closing this bug because I believe this was just a Verilator problem.

[colinschmidt]

It turns out the issue was actually that the verilator harness doesn't leave reset high for long enough (only about 10 cycles compared to 100+ for vsim). I'll push a commit to the hwacha branch fixing that issue.