Clean up handling of memory models. Rename MidasMemModel -> FASED

[davidbiancolin]

In preparation for presenting FASED at FPGA2019. Clean up memory system model handling.

• Removes simple latency pipe and CPU-hosted memory model
• Renames MidasMemModel -> FASEDMemoryTimingModel
• Updates readme to note staleness, redirect to docs.fires.im

Should not be RTL changing, but will regenerate AGFIs in FireSim.