ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

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FireSim/MIDAS 1.5.0 Dev PR #118

Closed davidbiancolin closed 5 years ago

davidbiancolin commented 5 years ago

This is the associated MIDAS PR for the FireSim 1.5.0 release. A summary of changes follows.

Major changes:

Brings up multi-channel host-dram support. #97
Pulls out target-annotations into a seperate scala project "targetutils" to break a circular dependency between MIDAS and Rocket-Chip. #106
- Many MIDAS components rely on RC utilites
- But we want to be able to use MIDAS annotations on Rocket Chip RTL
Reintroduces print synthesis from the DESSERT paper. #109
Cleans up handling of memory timing models in preparation for FPGA2019 #117

Other changes

116 - Fixed a bug in decoupled-channel implementations

114 - Allows memory timing model to be configured with a diplomatic edge, reducing user error when configuring functional models

110 - Moves common DMA functionality for widgets into a set of traits

105 - Adds address-range histograms to memory-timing model

104 - Fixes a bug in memory timing model latency histograms