Preliminary Golden Gate (MIDAS II) Support

[davidbiancolin]

This preliminary PR introduces support for MIDAS II, which we are naming Golden Gate (so named in our upcoming ICCAD2019 publication; we'll release a copy shortly).

Golden Gate is a rewrite of the front (~ target transformations & FAME1) and middle-ends (simulation mapping) of the MIDAS compiler, to support simulating target machines with multiple clock domains and to enable cycle-exact multi-cycle resource optimizations (the latter of which is the subject of our ICCAD2019 paper).

In order to support these goals, Golden Gate implements simulators a latency-insensitive bounded dataflow network. These networks can model combinational paths in the target machine that span multiple models (at the expense of FMR). To support this, we had to re-implement the FAME1 pass to generate unique token enqueue guards as function of the input ports each output port is combinationally dependent on.

TODOs:

• [x] Put legacy token initialization on a config switch - tied to black box endpoint system
• [x] New endpoint API -- see separate PR

Documentation TODOs:

• [x] Migrate README to FireSim RTD - PR to follow
• [x] Consider publishing scaladoc - open an issue
• [x] LI-BDN explanation - separate PR

[aswaterman]

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[davidbiancolin]

WIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIP

I think we're down to "WIIIP" now