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FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
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New snapshotting implementation
#18
Closed
donggyukim
closed
8 years ago
donggyukim
commented
8 years ago
Generate more understandable block rams(read-first mode)
Reference:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf
Reduce snapshotting overhead
Generate null tokens during target reset
donggyukim
commented
8 years ago
Validated with FPGA