ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
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Reorganize packages #21

Closed donggyukim closed 7 years ago

donggyukim commented 8 years ago

@davidbiancolin @jackkoenig

  1. Reorganize package & directory structures as follows:
  1. Capitalize file names, split files if necessary(e.g. daisy.scala).
  2. Clean up dead code revealed by this PR.
  3. Put misc(scripts) in resources.

I think it's almost ready to call this repo MIDAS.

davidbiancolin commented 8 years ago

This definitely feels like motion in the right direction. What remains before we can push it to ucb-bar/midas.git

It's not clear to me what you mean by "core: core chisel implementations(daisy chains, simulation wrapper, zynq shim)" At this point, it sort of feel like "everything else".

donggyukim commented 8 years ago

In my opinion, core contains core components of simulation necessary for simulation mapping. ZynqShim probably doesn't fit into this category, then we may move it to widgets.