Catapult

[donggyukim]

@davidbiancolin @sagark Finally, strober examples run in catapult with this branch. It didn't test this with midas-top because compiling riscv-fesvr is not trivial with visual studio. But, we may want to merge pywrite on top of this PR to move forward.

[aswaterman]

well done, @donggyukim !

[davidbiancolin]

Nice job, Donggyu. I've skimmed through most of this PR, but i think it would be really helpful if you summarized the major changes in the PR. This is a massive set of changes.

Some general concerns:

• Ifdef creep + hacks to support different host platforms (Windows vs Linux & Altera vs Xilinx)
• It feels like we are growing class hierarchies in ways that are convenient now, but not really make sense in the long run. This needs some justification before we hack on it further

[davidbiancolin]

I think we should just keep this a separate dev branch until we clean everything up post retreat.

[donggyukim]

Yeah, I agree that this PR is very hard to grasp. Here's my summary:

• 57b4db9: As the commit message says, I split ZynqShim into platform-agnostic target & widget interconnect FPGATop and platform specific interface ZynqShim. For nowFPGATop consists of AXI networks, which will be eventually ported with Tilelink2.
• 30143a5 ~ df76ce3: I implemented CatapultShim on top of FPGATop and its emulation. Here I assumed its communication is done with a large width serial link.
• ae9e9f8 ~ f3735ee: Unfortunately, the memory interface in catapult is broken, and thus, we need to direct memory transactions to software having memory models. These commits are my efforts to efficiently handle nasti memory transactions. We can optionally instantiate memory timing models or nasti I/O handlers for software. sim_mem is also provided in software when we instantiate a nasti I/O handler. Also, there non-blocking step to handle memory transactions during simulation ticks. The nasti I/O handler will back-pressure simulation fire when there are outstanding requests. This part can be further improved by pywrite.
• 363a720: I just noticed that Catapult provides the light-weight soft-register interface which matches FPGATop. Bulk PCIE communication has high overhead and is hard to manipulate.
• f899739 ~ 43ec7e0: Unfortunately, we have to compile software drivers with the compiler of Visual Studio and the library provided by Microsoft. We used linux-specific types and functions in many places. In makefile, I also had to tackle visual studio specific options with window specific paths. Strangely, windows use backslash as a path separator, which drove me crazy. Finally, I couldn't compile DRAMSim as it is, so I forked and edited it a little bit. It seems like the compiler is not as smart as gcc, causing wired linking errors for DRAMSim.

[donggyukim]

To answer @davidbiancolin's concerns:

• I don't need a lot of hack for Altera tools. One surprising thing is it doesn't define SYNTHESIS. This is why I fixed it in 8b9e10f.
• It's unavoidable to have ifdef in c++ code. Visual Studio and Windows have their own world which is not compatible with Linux and POSIX.
• I'm not sure what class hierarchy in this case, but if you mean splitting ZynqShim, I explained in the previous post.

[donggyukim]

In addition, I cannot assume that users will install Cygwin in the catapult node, so I should've supported Powershell with Gow by fixing makefile as in 83b90fa.