Master doesn't properly measure runtime, reports wrong simulation frequency

ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Other

97 stars 15 forks source link

Master doesn't properly measure runtime, reports wrong simulation frequency #27

Open davidbiancolin opened 7 years ago

davidbiancolin commented 7 years ago

For long running workloads we stuff like this:

==> spec-test/473.astar.test.err <==
SEED: 7282986
time elapsed: 18446744072974.2 s, simulation speed = 0.00 KHz
*** PASSED *** after 74901751853 cycles
Runs 74901751853 cycles
[PASS] MidasTop Test
SEED: 7282989

real    130m58.391s
user    0m0.237s
sys     0m0.526s

ccelio commented 7 years ago

Is that a 32-bit casting issue?

davidbiancolin commented 7 years ago

It certainly smells like it.

ccelio commented 7 years ago

I had to change the coremark source code (bad on me, I know) that handles printing out the timer... even though they provided define hooks to provide your own timer, they still fucking hardcoded the printf statement and got it wrong.

davidbiancolin commented 6 years ago

This is only a problem on zynq platforms; not F1.