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ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
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L2 cache model #33

Closed donggyukim closed 7 years ago

donggyukim commented 7 years ago

This implements a simple L2 cache model in SimpleLatencyPipe. We should generalize it later.

davidbiancolin commented 7 years ago

You should consider merging this into the sim-mem-cleanup branch. Or i can do that. There's a little overlap.

aswaterman commented 7 years ago

What L2$ does it model?

donggyukim commented 7 years ago

@aswaterman It just keeps tags and models a simple timing. Shorter latency is given if there's hit.

aswaterman commented 7 years ago

I see