Open edwardcwang opened 6 years ago
Passes midas-top:
$ make run-bmark-tests EMUL=vcs RISCV=$RISCV
cd /scratch/edwardw/midas-top/generated-src/f1/RocketChip2GExtMem/ && \
./MidasTop /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mm.riscv +sample=/scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mm.riscv.sample +max-cycles=100000000 +mm_MEM_LATENCY=10 \
2> /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mm.riscv.out && [ $PIPESTATUS -eq 0 ]
Chronologic VCS simulator copyright 1991-2016
Contains Synopsys proprietary information.
Compiler version L-2016.06-1_Full64; Runtime version L-2016.06-1_Full64; Nov 20 23:34 2017
[...]
Compiler version L-2016.06-1_Full64; Runtime version L-2016.06-1_Full64; Nov 20 23:37 2017
matmul(cid, nc, 16, input1_data, input2_data, results_data); barrier(nc): 46618 cycles, 11.3 cycles/iter, 1.5 CPI
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mm.riscv.out after 356158 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/spmv.riscv.out after 137278 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mt-vvadd.riscv.out after 111038 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/median.riscv.out after 24382 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/multiply.riscv.out after 56638 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/qsort.riscv.out after 342334 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/towers.riscv.out after 23230 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/vvadd.riscv.out after 17470 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/dhrystone.riscv.out after 251838 cycles
[ PASSED ] /scratch/edwardw/midas-top/output/f1/RocketChip2GExtMem/mt-matmul.riscv.out after 68286 cycles
(Don't merge until https://github.com/ucb-bar/midas/pull/50 is merged since this PR depends on it)