Fix dep warnings in memory model

ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

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Fix dep warnings in memory model #68

Closed davidbiancolin closed 6 years ago

davidbiancolin commented 6 years ago

This hushes up Chisel/Firrtl a bunch.

davidbiancolin commented 6 years ago

I checked this by diffing verilog; unfortunately fixing the autoclonetype dep warnings does change name generation so that one is hard to verify without simulation.