Merge in some host-memory system model bug fixes / QoL improvements

ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Other

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Closed davidbiancolin closed 6 years ago

davidbiancolin commented 6 years ago

DRAMsim based models now (better) respect AXI4 ID ordering requirements.

Tested by running the asm tests on boom and rocket in ML-simulation (with and without +dramsim).