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ucb-bar / midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
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[RFC] Initial multiclock support in token channels & synthesizable unit tests #90

Closed davidbiancolin closed 6 years ago

davidbiancolin commented 6 years ago

This is big change, but not one that should affect default FireSim targets. There are three major additions here, they can be factored into two different PRs if that's desired.

  1. Adds preliminary multiclock support in channels between the transformed-RTL and endpoints
    • Restricted to integer / reciprocal clock ratios
    • Channel generation introspects on endpoint clock-ratio during Simulation Mapping
  2. Adds synthesizable unittest generation framework
    • Derived from RocketChip's unittest package
    • Generator (App) lives in src/main/scala/midas
    • Makefrag lives in src/main/cc/unittest
  3. Reworks the build system for RTL simulation (MIDAS-level)
    • to share code between unittests, and MIDAS-level simulations
    • recipes for building VCS and Verilator simulators moved to src/main/cc/rtlsim