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Unable to boot linux using the rerocc in NoCConfig #4

Open RealJustinNi opened 8 months ago

RealJustinNi commented 8 months ago

Hello, I am attempting to configure a NOC within Firesim version 1.18.0 by utilizing rerocc, with a configuration featuring 5 Rocket cores and 10 Gemmini accelerators. Despite having successfully generated the bitstream, upon running the simulation, I encounter an issue where Linux fails to complete its boot process and stalls at the line: icenet: loading out-of-tree module taints kernel. Based on other log messages, it appears that there should be a subsequent step involving mounting /dev/iceblk as the root filesystem device. However, there seems to be a problem with this step. Could you kindly assist me in identifying the underlying cause? Many thanks in advance for your help.

class Gemmini10ReRoCCBaseConfig extends Config(
  //new chipyard.config.WithReRoCC(4, chipyard.rerocc.ReRoCCTileParams(dcacheParams=None, mergeTLNodes=true, l2TLBEntries=1024, l2TLBWays=4)) ++
  new chipyard.rerocc.WithReRoCC(chipyard.rerocc.ReRoCCClientParams(nCfgs=4) , chipyard.rerocc.ReRoCCTileParams(l2TLBEntries=512, l2TLBWays=4, mergeTLNodes=true)) ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new gemmini.DummyDefaultGemminiConfig ++
  new freechips.rocketchip.subsystem.WithNBigCores(5) ++
  new chipyard.config.WithSystemBusWidth(128) ++
  new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++
  new freechips.rocketchip.subsystem.WithNBanks(8) ++
  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=2, capacityKB=2048) ++ 
  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
  new chipyard.config.AbstractConfig)
jerryz123 commented 8 months ago

Can you provide more details on the versions of various repositories you are using?

RealJustinNi commented 8 months ago

firesim version : 1.18.0-0-g535dcdc29 gemmini version: v0.7.1-21-g8c8b38b rerocc version: this repo Codes that I modified in firesim:

  1. Copy your repo rerocc to firesim/target-design/chipyard/generators/chipyard/src/main/scala , rename the package-name rerocc to chipyard.rerocc.

  2. Add with chipyard.rerocc.CanHaveReRoCCTiles in firesim/target-design/chipyard/generators/chipyard/src/main/scala/DigitalTop.scala.

  3. Add the following code to firesim/target-design/chipyard/generators/chipyard/src/main/scala/config/NoCConfigs.scala.

    class Gemmini10ReRoCCBaseConfig extends Config(
//new chipyard.config.WithReRoCC(4, chipyard.rerocc.ReRoCCTileParams(dcacheParams=None, mergeTLNodes=true, l2TLBEntries=1024, l2TLBWays=4)) ++
new chipyard.rerocc.WithReRoCC(chipyard.rerocc.ReRoCCClientParams(nCfgs=4) , chipyard.rerocc.ReRoCCTileParams(l2TLBEntries=512, l2TLBWays=4, mergeTLNodes=true)) ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new gemmini.DummyDefaultGemminiConfig ++
new freechips.rocketchip.subsystem.WithNBigCores(5) ++
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++
new freechips.rocketchip.subsystem.WithNBanks(8) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=2, capacityKB=2048) ++ 
new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
new chipyard.config.AbstractConfig)

  4. Add the following code to firesim/target-design/chipyard/generators/chipyard/src/main/scala/config/RocketConfigs.scala though not used.

    class RocketReRoCCConfig extends Config(
new chipyard.config.WithReRoCC ++
new chipyard.config.WithAccumulatorRoCC ++
new chipyard.config.WithAccumulatorRoCC ++
new chipyard.config.WithAccumulatorRoCC ++
new chipyard.config.WithAccumulatorRoCC ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
new chipyard.config.AbstractConfig)

  5. Add the following code to firesim/target-design/chipyard/generators/firechip/src/main/scala/TargetConfigs.scala and use that config to build bitstream.

    class FireSimGemmini10ReRoCCConfig extends Config(
new WithDefaultFireSimBridges ++
//new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.Gemmini10ReRoCCBaseConfig)

    6.config_build_recipes.yaml

    firesim_rocket_5_gemmini_10_30mhz_xbar:
PLATFORM: xilinx_alveo_u200
TARGET_PROJECT: firesim
DESIGN: FireSim
TARGET_CONFIG: FireSimGemmini10RocketConfig
PLATFORM_CONFIG: BaseXilinxAlveoU200Config
deploy_quintuplet: null
platform_config_args:
    fpga_frequency: 30
    build_strategy: TIMING
post_build_hook: null
metasim_customruntimeconfig: null
bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u200.yaml