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ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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Synchronous read? #40

Closed AwaniK closed 2 years ago

AwaniK commented 3 years ago

Do the memory and regfile have synchronous read operation?

ekiwi commented 2 years ago

Do the memory and regfile have synchronous read operation?

The regfile is using a combinatorial read memory. The cache uses a synchronous read memory.

Changing the read latency on the register file would require some pipeline changes.