Upgrade to Latest RISC-V Spec

[vighneshiyer]

Resolves #29. Still WIP:

• [X] Update CSR implementation to match latest spec
• [X] Unify hex files for Scala and verilator tests
• [X] Modify the magic memory model to load program at DRAM base
• [ ] Debug test failures manually via waveform
• [ ] Modify the verilator testbench to snoop the dcache request bus to look for tohost writes
• [ ] Modify Makefile to compile and use tests in riscv-tests
• [ ] Support "syscall" API used in riscv-tests/benchmarks