Chisel improvements - Githubissues

ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

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Chisel improvements #51

Closed ObiWanRohan closed 2 years ago

ObiWanRohan commented 2 years ago

Added bundles for pipeline registers
Changed cascaded Mux to MuxCase
Added multithread use to verilator
Added new testQuick command to makefile to only run previous failed test cases

ekiwi commented 2 years ago

This looks great!

Only the register initialization now looks a little more noisy. Could you try to investigate whether Bundle Literals could be used to do the initialization?

ObiWanRohan commented 2 years ago

Bundle Literals can be used for the initialisation. I hadn't used them since they are still experimental.