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ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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Is this a BUG in TileTester.scala? #52

Closed LingZichao closed 1 year ago

LingZichao commented 1 year ago

https://github.com/ucb-bar/riscv-mini/blob/d3bfaf99bbd778028e92b402cbf55035f07230ff/src/test/scala/mini/TileTester.scala#L88

In my view,aw shall be ar , which stands for read address channel in AXI

ekiwi commented 1 year ago

Could be. What happens if you change it?

LingZichao commented 1 year ago

Uhhh ... Because there is no out-of-order transaction , so it just maybe a ctrl c+v bug and no negative impact. : )

ekiwi commented 1 year ago

Uhhh ... Because there is no out-of-order transaction , so it just maybe a ctrl c+v bug and no negative impact. : )

feel free to still make a PR. Seems like something that should be fixed