ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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Strobe writes broken in TileTester. #56

Open jdeters opened 1 year ago

jdeters commented 1 year ago

The way that strobe writes are implemented in TileTester.scala is broken. As it is now, it creates a Wire 70 bits long and writes junk data to the testing memory. I fixed with the following lines of code:

val blastBytes = nasti.dataBits / 8
val write = (VecInit.tabulate(blastBytes)(byte => (Mux(dut.io.nasti.w.bits.strb(byte), dut.io.nasti.w.bits.data, _mem(addr + off)))(8 * (byte + 1) - 1, 8 * byte))).asUInt

I don't know if this would be the preferred fix, but I just wanted to let you all know.