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ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`? #60

Closed Stevengre closed 3 weeks ago

Stevengre commented 5 months ago

I'm trying to generate either a Tile.fir or Tile.mlir file in the generated-src directory after running the make command. However, I'm facing an issue.

Here's what I've done so far:

I ran make in the terminal as usual. Then, I tried changing emitSystemVerilogFile to emitCHIRRTL in the code. After that, I executed sbt 'runMain mini.Main'. Despite these steps, I'm not seeing the expected Tile.fir or Tile.mlir files in the generated-src directory. It's quite puzzling for me.

Thanks in advance for any help or guidance you can provide!

Yakkhini commented 4 weeks ago

Go to see https://github.com/ucb-bar/riscv-mini/pull/67 which modify Makefile and pass an argument --dump-fir to ChiselStage. emitSystemVerilog(File) is just a common API to generate something like SV or Firrtl file so there is no need to modify source code.