Problems related to asSint type conversion to verilog file (.sv)

in the version chiselVersion = "5.0.0" chiseltestVersion = "5.0.2" version riscvmini: the code in datapath

` val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)(
    Seq(
      LD_LH -> lshift(15, 0).asSInt,
      LD_LB -> lshift(7, 0).asSInt,
      LD_LHU -> lshift(15, 0).zext,
      LD_LBU -> lshift(7, 0).zext
    )
  )`

the Sint target trans to .sv lead to

'wire [3:0][32:0] _GEN =
    {{{1'h0, _csr_io_out}},
     {{1'h0, ew_reg_pc + 32'h4}},
     {ld_type == 3'h5
        ? {25'h0, lshift[7:0]}
        : ld_type == 3'h4
            ? {17'h0, lshift[15:0]}
            : ld_type == 3'h3
                ? {{25{lshift[7]}}, lshift[7:0]}
                : ld_type == 3'h2
                    ? {{17{lshift[15]}}, lshift[15:0]}
                    : {1'h0, io_dcache_resp_bits_data}},
     {{1'h0, ew_reg_alu}}};'

and the width of regfile should be 32 ,but it is 32 .it predict width of sint to 33 ,with log : ' chisel3.package$ChiselException: Connection between sink (Datapath.load: Wire[UInt<32>]) and source (Datapath.load_?: OpResult[SInt<33>]) failed @: Sink (UInt<32>) and Source (SInt<33>) have different types'

and i find the old riscv-mini verion which has sbt

`ThisBuild` / scalaVersion     := "2.13.7"
ThisBuild / version          := "2.5.0"
ThisBuild / organization     := "edu.berkeley.cs"'

it trans to file v with the same chisel code and the code is :

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [63:0] _RAND_14;
...
  wire [32:0] load = 3'h5 == ld_type ? $signed({{24{_load_T_8[8]}},_load_T_8}) : $signed(_load_T_14); // @[Mux.scala 81:58]
  wire [32:0] _regWrite_T = {1'b0,$signed(ew_reg_alu)}; // @[Datapath.scala 203:18]
  wire [31:0] _regWrite_T_2 = ew_reg_pc + 32'h4; // @[Datapath.scala 204:48]
  wire [32:0] _regWrite_T_3 = {1'b0,$signed(_regWrite_T_2)}; // @[Datapath.scala 204:55]
  wire [32:0] _regWrite_T_4 = {1'b0,$signed(csr_io_out)}; // @[Datapath.scala 204:82]
  wire [32:0] _regWrite_T_6 = 2'h1 == wb_sel ? $signed(load) : $signed(_regWrite_T); // @[Mux.scala 81:58]
  wire [32:0] _regWrite_T_8 = 2'h2 == wb_sel ? $signed(_regWrite_T_3) : $signed(_regWrite_T_6); // @[Mux.scala 81:58]
  wire [32:0] regWrite = 2'h3 == wb_sel ? $signed(_regWrite_T_4) : $signed(_regWrite_T_8); // @[Datapath.scala 205:7]

but i think the width of it is 32 is more suitable for sint .so prehaps how can i get some skill to make it to 32 ? thank you

ucb-bar / riscv-mini

Problems related to asSint type conversion to verilog file (.sv) #66