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ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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Fix: Default make recipe not dump firrtl file. #67

Closed Yakkhini closed 6 months ago

Yakkhini commented 6 months ago

According to README in riscv-mini, running make would dump .fir firrtl file and .sv file. But there is only a SystemVerilog file output in the generated dir.

Some projects maybe relies to this behavior to work, such as ussc-vama/essent-chisel-gallery.

So I append a flag to SBT to avoid some potential issue. Running make will also generate firrtl file now.