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ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel
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Store misaligned exception with the subsequent instruction's write request not flushed #71

Open SeddonShen opened 3 months ago

SeddonShen commented 3 months ago 
Addr                   Instruction                   Hex
00000200         addi x1, x1, 4               00408093
00000204         sw x0, 2(x0)                00002123
00000208         sh x1, 32(x2)               02111023
0000020c         addi x1, x1, 4               00408093

If run the instructions above, the second sw instruction will bring a misaligned exception, the following sh instruction is not flushed correctly, causing the CPU to still send a write request to memory. This results in MEM[000000020] <= 0000000004.

I enabled trace in the source code and replaced rv32ui-p-p-simple.hex below to execute CoreSimpleTests. 


000000000000000000010101464c457f
00000034000001000000000100f30002
00280001002000340000000000000454
00000000000000000000000100020005
00000005000002600000026000000000
00000000000000000000000000002000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
07ff0c6334102ff3158f0f1300000f17
00000f17020f1863ef0f0f1300000f17
0540006fed9ff06f000f0463ee4f0f13
00000013000000130000001300000013
0000001330500073fa0f5ee334202f73
00000013000000130000001300000013
00000013000000130000001300000013
00000013000000130000001300000013
00000013ffdff06f780e1073539e6e13
00000013000000130000001300000013
00000013000000130000001300000013
00000013000000130000001300000013
fbff0ce334102ff3098f0f1300000f17
e25ff06f000f0463e30f0f1300000f17
000000130000001300000013fa1ff06f
00000013000000130000001300000013
00408093021110230000212300408093
00000e130400006f00100e130ff0000f
1012907300028463de02829300000297
01428293000002973002b0731f800293
0ff0000f10000073f100257334129073
ffdff06f000000730040006f00100e13
00000000000000000000000000000000
00000000000000000000000000000000

From the trace, it is evident that an unintended write request was issued.

INST[000000200] => 00408093
PC: 00000000, INST: 00000013, REG[  0] <- 00000000
INST[000000204] => 00002123
PC: 00000000, INST: 00000013, REG[  0] <- 00000000
INST[000000208] => 02111023
PC: 000001fc, INST: 00000013, REG[  0] <- 00000000
INST[00000020c] => 00408093
MEM[000000000] <= 0000000000
PC: 00000200, INST: 00408093, REG[  1] <- 00000004
INST[0000001c0] => 00000f17
**MEM[000000020] <= 0000000004**
PC: 00000204, INST: 00002123, REG[  0] <- 00000000
INST[0000001c4] => 098f0f13
PC: 00000204, INST: 00002123, REG[  0] <- 00000000
INST[0000001c8] => 34102ff3
PC: 0000020c, INST: 00000013, REG[  0] <- 00000000
INST[0000001cc] => fbff0ce3