Closed michg closed 9 years ago
Hi, I did a quick check and tried a modified version of your example:
object hello { def main(args: Array[String]): Unit = { chiselMain( ArrayString, () => Module(new Zscale(), {case coreInstBits => 32}) ) } }
Unfortunately this just results in another exception:
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=384m; support was removed in 8.0
[info] Set current project to zscale (in build file:/home/boehmers/projects/zscale/)
[info] Running zscale.hello
error java.lang.ClassCastException: java.lang.Integer cannot be cast to java.lang.Boolean
java.lang.ClassCastException: java.lang.Integer cannot be cast to java.lang.Boolean
at scala.runtime.BoxesRunTime.unboxToBoolean(BoxesRunTime.java:90)
at rocket.CoreParameters$class.$init$(core.scala:45)
at rocket.CoreModule.
I am not an expert when it comes to chisel parameters. However it seems like there are unused thus undefined parameters in code imported from the rocket and uncore projects. This causes cast exceptions. Hacking one leads to the next... :-(
It would be nice to have a Makefile generating the C++ emulator and Verilog code as starting point just like for the sodor cores.
Regards, Stephan
Woops, I was going to post this message here:
The chisel version of Z-scale shares code from the rocket repository and the uncore repository, and therefore you need to instantiate the Z-scale design from rocket-chip. I'm still currently refactoring the rocket-chip repository so that the Z-scale design shares the same testbench with the rocket design, but in the mean time, please follow the directions below to instantiate Z-scale Verilog. Once everything is sorted out, I was going to write a blog post about this, so please stay tuned.
$ git clone https://github.com/ucb-bar/rocket-chip.git $ cd rocket-chip $ git submodule update --init
You need a matching riscv-tools compiled for now, if you don’t have it, you can build it with the following instructions:
$ mkdir install
$ export RISCV=pwd
/install
$ cd riscv-tools
$ git submodule update --init --recursive
$ ./build.sh
— wait for a while —
if you have any problems, please consult documentation on https://github.com/riscv/riscv-tools/tree/new_privileged_isa
Once you’ve done this, you can go ahead and compile Verilog with:
$ cd vsim $ make MODEL=ZscaleTop verilog
The resulting file should be sitting inside the generated-src directory.
ZscaleTop has more things than you want probably, you may want to look at ZscaleSystem (core + buses) and/or Zscale (the core itself).
Top-level glue code sits here: src/main/scala/ZscaleChip.scala Top-level Z-scale module can be found here: zscale/src/main/scala/zscale.scala
Best, -Yunsup
One quick correction, with the new refactoring on rocket-chip, you'll have to use "make CONFIG=ZscaleConfig MODEL=ZscaleTop verilog" instead.
Thanks for the update! I will have a look at this. I never tried the rocket. Happy to see a lower end RISCV so I might lay to rest my VHDL implementation.
Ok, worked for me!
Thanks a lot! Stephan
Thanks a lot for your reply. I will give it a try in the next days.
Yunsup,
What happened to the ZscaleConfig file now? It's not there anymore. I got the following error messages when I tried to generate Zscale.
Nhon
Running rocketchip.Generator /home/nhon/rocket-chip/vsim/generated-src rocketchip ZscaleTopverilog rocketchip ZscaleConfig error java.lang.Exception: Unable to find part "rocketchip.ZscaleConfig" from "ZscaleConfig", did you misspell it? java.lang.Exception: Unable to find part "rocketchip.ZscaleConfig" from "ZscaleConfig", did you misspell it?
Hello zscale-developers, could you provide some additional information, how to convert the scala sources to verilog? Adding the following main in zscale.scala results in Chisel. ParameterUndefinedException: Parameter CoreInstBits undefined. object hello { def main(args: Array[String]): Unit = { chiselMain(ArrayString, () => Module(new Zscale())) } Thanks a lot for your feedback.