Wait state for first transfer when previous transfer was IDLE

[boehmerst]

Hi all, to me it seems like in the HASTI implementation the very first transfer, when coming from idle, results in a wait state issued to the master even so the slave is actually ready. This is caused by the s1_grants register is deasserted because no requests and so no grants have been asserted before. In other words: The initial address phase gets stalled for one cycle (but will be latched according to AHB-Lite standard) because the previous but actually not real data phase is considered stalled (in.hreadyout is low) since no slave was selected. Can anyone confirm this behaviour?

(io.ins zipWithIndex) foreach { case (in, i) => { val g1 = s1_grants(i) in.hrdata := dgate(g1, io.out.hrdata) in.hreadyout := io.out.hreadyout && g1 in.hresp := dgate(g1, io.out.hresp) } }

Best, Stephan

[yunsup]

Hi Stephan,

You're right. I wanted to first get a version out that is functionally correct, while we're working on a version with better performance.

-Yunsup

[yunsup]

Please try out commit d39e651d30de8e34b509b68775bef854401eec97. This should get rid of the performance problem you've been seeing. There's one more inefficiency in the HASTI bus I want to squeeze out. Stay tuned.

[yunsup]

I've squeezed out more cycles on the HASTI bus. Please try out commit a60954cef6de11b7cb9f9a3474fa229074fa9639. I'll wait until you had a chance to try it out before closing the issue.

[boehmerst]

Ok thanks, I'll give it a try asap! I know AHB-Lite has quite some painful corner cases since it was initially intended for lightweight single master multi slave architectures!

[boehmerst]

Hi Yunsup, I checked your commit and can confirm the updateded version serves the first transfer wirhout a wait state being issued. I will do some more regressions on hasti the next days.

Thanks, Stephan

[yunsup]

Cool let me know if you find any problems.