The current version of vitis implements FIFO fullness checks by de-referencing the indexes more than once. Since the indexes are declared as volatile, this results in the pointers being read multiple times. At a minimum, this requires a memory load from the L1D cache to occur.
It is possible for the indexes to change between the multiple accesses. This should not impact the operation of the single producer/single consumer FIFO but may cause multiple cache coherency events to occur which would slow down operation.
cyarp
commented
4 years ago
The current version of vitis implements FIFO fullness checks by de-referencing the indexes more than once. Since the indexes are declared as volatile, this results in the pointers being read multiple times. At a minimum, this requires a memory load from the L1D cache to occur.
It is possible for the indexes to change between the multiple accesses. This should not impact the operation of the single producer/single consumer FIFO but may cause multiple cache coherency events to occur which would slow down operation.