ucb-cyarp / vitis

Laminar - Optimizing DSP Compiler
BSD 3-Clause "New" or "Revised" License
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ClockDomain Discovery Fails when I/O Input is Directly Connected to RateChange Output #44

Open cyarp opened 4 years ago

cyarp commented 4 years ago

Discovery assumes that the input is coming from outside the clock domain and infers that the RateChange is an input. This is actually ambiguous but can be resolved by either defining the rates of the different I/O lines or by looking at other rate change nodes.

A workaround is to insert a dummy node in the clock domain that the input goes through before reaching the RateChange node.