ucb-cyarp / vitis

Laminar - Optimizing DSP Compiler
BSD 3-Clause "New" or "Revised" License
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Matlab FSM Code Generation Error when 2 FSMs are Directly Connected #45

Open cyarp opened 4 years ago

cyarp commented 4 years ago

It appears that there is now a bug with the Stateflow FSM code generation in Simulink when two FSMs are directly connected. If the names of the ports differ, the destination FSM's port name may be changed in the emitted Input Structure created by Simulink Coder. This appears to be a Matlab bug but I can investigate further.

A workaround is to insert a dummy node between the FSMs (ex. a delay with 0 delay).