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high-performance RTL simulator
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Using essent with Chipyard #20

Closed mayyxeng closed 6 months ago

mayyxeng commented 1 year ago

Hi,

I would like to use essent with the Chipyard project to speedup simulation (compared to verilator) of some SoC designs. I am using Chipyard v1.10.0 and it seems like the generated .fir files cannot be processed by essent.

> essent chipyard.harness.TestHarness.chipyard.example.simulation.SmallRocket2x2CoreMeshConfig.fir -O0 --parallel 2
line 1:0 missing 'circuit' at 'FIRRTL'
line 1:7 mismatched input 'version' expecting ':'
Exception in thread "main" firrtl.SyntaxErrorsException: 2 syntax error(s) detected

I tried to comment out the first line that errors out, but then something goes wrong with printf and assert statements during parsing. Commenting out those also did not resolve the issu chipyard.example.simulation.SmallRocket2x2CoreMeshConfig_all_sources.tar.gz e and some other error popped up.

I am not very familiar with the state of tooling with firrtl, but I noticed that v1.10.0 switched to circt's firtool (as opposed to the original Scala based firrtl). Does this mean that Chipyard is kind of unsupported for now?

I have attached the generated files in case you wanted to reproduce the error or take a look at the .fir files. chipyard.example.simulation.SmallRocket2x2CoreMeshConfig_all_sources.tar.gz

Thanks!

haoozi commented 10 months ago

Hi,

This error is due to incompatible FIRRTL version. Currently we are on FIRRTL 1.4.3 (see build.sbt) while chipyard 1.10 requires FIRRTL 1.5.6 (Chisel 3.5.6, from release note). Different output format and some different IR nodes lead to such error.

I'm not familiar with chipyard, if it has multiple clock domains then ESSENT may also fail, as it currently only supports one clock domain.

We are now working on bumping FIRRTL version to 1.5.6, which could resolve the incompatibility issue. However that doesn't guarantee chipyard will work out-of-box, some customization may be needed to remove multiple clock domains (if any) and external SystemVerilog file, IO pins could be another concern (for example, analog IO).

Hope that answers your question.

Best

sbeamer commented 7 months ago

Following up, 2 months ago, we pushed support for FIRRTL 1.5.6 to essent