Bump up FIRRTL to 1.5.6, the last SFC (Scala FIRRTL Compiler) before MFC (MLIR FIRRTL Compiler).
Bump up json4s to satisfy FIRRTL 1.5.6 dependency.
Bump up Scala to satisfy FIRRTL 1.5.6 dependency.
Bump up sbt for more recent JDK support.
Add a new pass to remove formal and coverage IR nodes.
Invoke firrtl.passes.memlib.VerilogMemDelays to align the behavior of MemRead.
Invoke firrtl.transforms.formal.ConvertAsserts to transform assertions (Verification IR nodes with op == Formal.Assert) into combination of Print and Stop statements.
Fix expected result of ReplaceRsvdKeywords pass test.
Compilation passed under JDK11 and JDK 17, also on JDK21 if further bump sbt to 1.9.0
Correctly generates header file for RocketChip (Both Chisel 3.5.6 and 3.4.3), simulation (dhrystone) passed.
Bump up FIRRTL to 1.5.6, the last SFC (Scala FIRRTL Compiler) before MFC (MLIR FIRRTL Compiler). Bump up json4s to satisfy FIRRTL 1.5.6 dependency. Bump up Scala to satisfy FIRRTL 1.5.6 dependency. Bump up sbt for more recent JDK support. Add a new pass to remove formal and coverage IR nodes. Invoke
firrtl.passes.memlib.VerilogMemDelaysto align the behavior of MemRead. Invokefirrtl.transforms.formal.ConvertAssertsto transform assertions (Verification IR nodes with op == Formal.Assert) into combination of Print and Stop statements. Fix expected result ofReplaceRsvdKeywordspass test.Compilation passed under JDK11 and JDK 17, also on JDK21 if further bump sbt to 1.9.0 Correctly generates header file for RocketChip (Both Chisel 3.5.6 and 3.4.3), simulation (dhrystone) passed.