ucsdsysnet / Rosebud

Framework for FPGA-accelerated Middlebox Development
MIT License
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Very rarely a slot is returned to the LB which was supposed to be in LB and not the RPUs. #2

Open mkhazraee opened 2 years ago

mkhazraee commented 2 years ago

When the packets are going through the system and from host the cores are reset and instructions are loaded, sometimes core wrappers observe slot error, when they see an incoming packet with a slot number which they are already operating on. This might be requiring more timeouts for the cores to flush their packets, or the packets to go through the system and release the slot.

Current remedy is to reset the board with the pci_reset script and reload the board.

mkhazraee commented 1 year ago

It did happen once when board was just programmed, so it's not only warm reload. Few notes: