Implement a DMA controller to support MOVE and XMOVE operations in CP/M 3 BIOS

[dmcnaugh]

I've looked at the Zilog 8410, popular in the period but unable to address banked memory or more then 64K of linear memory. The design and use of the I/O registers is also more complex than required for this task.

I propose using using memcpy() on the host side to perform the data transfer, and setup the DMA request via a series of I/O ports from the guest side, or possibly sequential writes to the same port to save I/O address space on the guest.

This would enable CP/M 3 to use more banks for buffers, give up a little more memory to the TPA space, and run a little faster.

[EtchedPixels]

You can do bank to bank copies with a Z80 DMA - the Altos 5 does for example. You can tell CPU v DMA bus cycles and you can tell read v write. It's a pig of a chip to emulate though. The 8237 is a lot easier to emulate, was 8080 compatible and can be used the same way. In fact it's a lot more powerful in some ways as it's got multiple channels.

CP/M 3 also gives you a scratch space in common memory so you can implement the copies with two DMAs, which is still a fair bit faster than the Z80 and way faster than 8080.

Alternatively the classier 8080 copiers do so for fixed sizes and borrow SP for the copying. That lets you get the copying rate somewhere more reasonable as you can load 4 bytes via HL, switch, push them, switch bank and if you unroll it for the normal sizes (FCB, partial FCB, 128 byte etc) and self modify the mvi a,#n values for the banks it's not too horrible.

[dmcnaugh]

A PR for your consideration, but still a work in progress.

[udo-munk]

I have some doubts that one could interface a Zilog DMA with the Intel 8080 CPU, the Zilog chips contain refresh for dynamic RAM, while the Intel chips don't, and need external circuits for this.

I had a look at the Intel 8257 DMA data sheet, this one can't do memory-to-memory operations, unusable. Only the later 8237 can do and can be interfaced with an 8080 CPU.

Then the CP/M 3 system guide says: If the physical record size of the media associated with a DPH is 128 bytes, you can set the DTABCB field of the DPH to OFFFFH, because in this case, the BOOS does not use a data buffer.

I set the DTABCB field to 0FFFEH and ran cpmgen, it still won't ask about data buffers, so the manual is right.

There is no point to implement this on such old hardware for CP/M 3, because it won't be used at all. Also for the IMSAI an implementation of a DMA circuit should be a real one, and not one made up, it never could be implemented in a real machine. For experimenting with made up circuits one better uses the cpmsim emulation, because it is build from all made up circuits anyway. Still won't change anything for CP/M 3, because it uses 128 bytes sectors on all disks.

[EtchedPixels]

The Zilog devices are near impossible to interface to non Z80 chips as they take shortcuts based upon the Z80 behaviour. I ended up using 16x50 and making 82C54 boards for my 8085 RC2014 system for that reason. Refresh cycles are the least of the problems.

[udo-munk]

Not emulating a real circuit and CP/M 3 with physical sector size 128 bytes won't use data buffers.