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ufrisk / pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
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Modifying CFG space #129

Closed Haseeb18P closed 1 year ago

Haseeb18P commented 1 year ago

Hey, is it possible to modify blocks 40, 60 & 70 in the cfg space? Would you be able to give me any instructions on how I can achieve this?

ufrisk commented 1 year ago

I know people have been modifying the .xci file directly that generates the PCIe core. Also the generated core sources.

But I have not looked into this myself so I can't really help more than this in this matter.

Haseeb18P commented 1 year ago

Would you happen to know the exact name of the .xci file that generates the PCIe core?

ufrisk commented 1 year ago

https://github.com/ufrisk/pcileech-fpga/blob/master/PCIeSquirrel/ip/pcie_7x_0.xci

Haseeb18P commented 1 year ago

After looking at the documentation on xilinx, it seems like that the MSI Control is stored at the 40 range, does this also seem like I'm looking in the right direction too you? Thanks in advance! image

ufrisk commented 1 year ago

Yeah, looks ok to me. This is a long and tedious process though, but best wishes with it 👍