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ufrisk / pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
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hi, how can i change here from config space in core_top file? #142

Closed xingkong158 closed 10 months ago

xingkong158 commented 1 year ago

image hi, Ulf i dont know why, i cant find somewhere to let it be changed, can you tell me where can change it?

ufrisk commented 1 year ago

Hi,

I'm sorry, but I actually haven't looked into extreme customizations of the PCIe core on this level. For the use cases I had it's been sufficient to do simpler customizations.

Some ideas though. If these values exist in the "DRP" debug port you may be able to override these values before the PCIe core is brought online by the PCILeech firmware.

Also, others have edited the PCIe core verilog source code files to achieve a pretty much full customization, so it's certainly possible. I haven't done this though.

Sorry for not being able to give a better answer than this right now :\

xingkong158 commented 11 months ago

hi brother, i just want to ask you how to do this config space? [image: image.png] it is different normal devices config space right?

Ulf Frisk @.***> 于2023年9月2日周六 17:07写道：

Hi,

I'm sorry, but I actually haven't looked into extreme customizations of the PCIe core on this level. For the use cases I had it's been sufficient to do simpler customizations.

Some ideas though. If these values exist in the "DRP" debug port you may be able to override these values before the PCIe core is brought online by the PCILeech firmware.

Also, others have edited the PCIe core verilog source code files to achieve a pretty much full customization, so it's certainly possible. I haven't done this though.

Sorry for not being able to give a better answer than this right now :\

— Reply to this email directly, view it on GitHub https://github.com/ufrisk/pcileech-fpga/issues/142#issuecomment-1703772359, or unsubscribe https://github.com/notifications/unsubscribe-auth/AO5VAJI76QB7UWHGKK4UGRTXYLZOJANCNFSM6AAAAAA4HBLMPU . You are receiving this because you authored the thread.Message ID: @.***>

ufrisk commented 11 months ago

I have not looked into changing those specific bytes, but as I mentioned it's probably possible to do that by using the "DRP" debug port or by editing the PCIe core either the verilog files or the .xci file.

You could look into this setting and similar ones to see if it's of any help: https://github.com/ufrisk/pcileech-fpga/blob/e13b8378e6d2d271a70b5e5c687e8e52fa368f09/PCIeSquirrel/ip/pcie_7x_0.xci#L428C119-L428C119