search

ufrisk / pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
913 stars 206 forks source link

zdma ip core seems to be broken #169

Closed YideTian closed 7 months ago

YideTian commented 7 months ago

running vivado_generate_project_100t.tcl raise an error:

CRITICAL WARNING: [filemgmt 20-984] The source file 'ZDMA/100T/ip/bram_pcie_cfgspace.xci' cannot be added to the fileset 'sources_1'. WARNING: [IP_Flow 19-395] Problem validating against XML schema: : Unexpected end of message CRITICAL WARNING: [IP_Flow 19-5097] Unable to determine VLNV from IP file; verify it has the correct syntax: ZDMA/pcileech_tbx4_100t/pcileech_tbx4_100t.srcs/sources_1/ip/bram_pcie_cfgspace/bram_pcie_cfgspace.xci ERROR: [Common 17-107] Cannot change read-only property 'synth_checkpoint_mode'. Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.

YideTian commented 7 months ago

I'm sorry. I didn't notice that vivado 2023.2 is required. I'm using vivado 2020.2.