Why using 7 Series FPGAs Integrated Block for PCI Express ip core instead of others?

[FlyingCatSSS]

Hello, I am recently learning the use of some PCIe ip cores for Xilinx FPGAs.There are two PCIe ip cores provided by Xilinx that is possibly be used in pcileech-fpga.One is the 7 Series FPGAs Integrated Block for PCI Express,which is adopted by your project,and apparently,is more complex,needs more knowledge of TLP packet details.The other is AXI Memory Mapped to PCI Express,which has axi memory mapped interface.If I want to use this ip core I only have to master axi protocol knowledge,free of PCIe protocol.I want to ask why you choose to use 7 Series FPGAs Integrated Block for PCI Express ip core instead of AXI Memory Mapped to PCI Express ip core.Is there some features in 7 Series that is vital to dma data transfer?

[ufrisk]

PCILeech started out as a research project. Being able to send/receive TLPs for reasons other than DMA was interesting as well. The 7 Series FPGAs Integrated Block for PCI Express was selected due to this.

Then there was a working implementation so I never really looked into the AXI memory mapped block.

The integrated block is more flexible as well, so I think the correct choice was made. But nothing is preventing you from trying on the memory mapped block. Using that would mean a completely different implementation on the software side though so I imagine there would be a bit of work involved.