search

ufrisk / pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
913 stars 206 forks source link

Failed to launch run 'impl_1' due to failures in the following run(s): bram_pcie_cfgspace_synth_1 #58

Closed xNarkon closed 4 years ago

xNarkon commented 4 years ago

Hello,

I have a problem while trying to build firmware ... I'm using Vivado 2020.1

I customized the Vendor and Device Identifiers by following: image

And while building after a while I'm getting this error: ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s): bram_pcie_cfgspace_synth_1 These failed run(s) need to be reset prior to launching 'impl_1' again.

What can be wrong?

ufrisk commented 4 years ago

It may be due to the wizard unchecking some stuff on other pages - like the config space things when altering the values.

image

xNarkon commented 4 years ago

Thanks for reply @ufrisk

I think it's some kind different situation, I don't why but it cannot find this bram_pcie_cfgspace image

The only things I changed in Vivado 2020.1 Wizard were these vendor & device ids :/

It looks like Vivado 2020.1 has a problem with loading: [IP_Flow 19-182] Failed to load BOM file '[REDACTED]/pcileech-fpga/ScreamerM2/pcileech_screamer_m2/pcileech_screamer_m2.srcs/sources_1/ip/bram_pcie_cfgspace/bram_pcie_cfgspace.xml'.

Also got this warning: WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'spirit:order' : Invalid value format for this type

*** Running vivado
    with args -log bram_pcie_cfgspace.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source bram_pcie_cfgspace.tcl

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source bram_pcie_cfgspace.tcl -notrace
Command: synth_design -top bram_pcie_cfgspace -part xc7a35tcsg325-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tcsg325-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 160156
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.594 ; gain = 0.000 ; free physical = 4707 ; free virtual = 26004
---------------------------------------------------------------------------------
ERROR: [Synth 8-439] module 'bram_pcie_cfgspace' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.594 ; gain = 0.000 ; free physical = 4750 ; free virtual = 26048
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
6 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 10:46:37 2020...
xNarkon commented 4 years ago

I found an issue, running bitstream building from Vivado itself is somehow broken, when made it run from the console, everything went flawlessly.