ufrisk
commented
1 year ago Hi, Those parts are controlled by the Xilinx IP core. You'd have to configure the Xilinx IP core in ways that allow you to change this.
It's possible by either using the wizard or changing values manually in the .xci file, or even more advanced in the verilog sources.
Unfortunately there is no other good way. As you mention it's not efficient, but it is how it is...
Do you know how to change the pcie configuration space between 0x40-0x60? It seems that it has not been changed through the. coe file. Some people say that it can be changed by manually editing the xilinx ip. It does work, but I don't think this is an effective method. Is there any other ways？