ujamjar / hardcaml

[Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml
https://github.com/janestreet/hardcaml
ISC License
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Support unknowns #5

Open andrewray opened 9 years ago

andrewray commented 9 years ago

To allow synthesis more optimization opportunities.

Considering adding constu "11--0" and maybe umux (with default u's). Something like casex/casez might also be required, along with support for parallel_case/full_case.

Then need to figure out what to do in simulation which will need to model multi-value logic.