Closed chriskmanx closed 8 years ago
Sorry, I wasn't clear if you wanted to do this in the notebook or not. I will assume not for now (although this will all work in a notebook, its just a bit more involved to get nice integration).
So, the first thing is you will need a testbench. I will assume you already have this and are using values from a module labelled B
to drive it (ie Bits.Comb.IntbitsList or somesuch).
The easiest way to proceed is;
module Vcd = Vcd.Make(B)
Then you need to find the simulation datastructure and wrap it ie
let sim = ....whatever builds the simulator...
let sim = Vcd.wrap (output_string stdout) sim in ...
note; if you write to a file rather than stdout, then remember to close it at the end!
This will write a .vcd file which you can view with standard waveform viewers such as gtkwave.
Alternatively, you could have a play around with https://github.com/ujamjar/hardcaml-waveterm. For an example see;
(setup)
(wrap simulator)
(display)
Thanks Andy
I must admit on my first reading of your issue your mention of .wave
files passed me by - I'd totally forgotten about them, and the related waveterm
and wavedraw
applications!
The reason is they were written to test the library until it could be used interactively with testbenches (as shown in the example above). That said, so far as I can see, if you want you can use these applications and .wave files if you want. I should warn you, however, that they are a horribly inefficient way of storing wave data. There is some nice html rendering functionality provided though.
To expand a bit further, you have a few choices to see waveforms with hardcaml
Vcd_ext.Make(B).gtkwave
runs gtkwave without an intermediate file _(hint; readline() after the sim)
Hello Andy,
I have created a simple Hardcaml project and would like to simulate it using waveterm ex iPython notebook. I have a circuit that I can generate via "HardCaml.Rtl.Verilog.write (output_string stdout) circuit" and I can verify its functionality using shallow embedding and bit lists as well as compile the Verilog through to a netlist. My present cicruit is purely combinatorial logic but once I proceed to sequential logic I will need to simulate. So how do I go from here to using waveterm? From looking at the code I need to generate .wave files. My ultimate goal is to create the wave output in ASCII such that I can construct test cases comparing output against known values.
Thanks and best Regards
Chris Kohlhepp