Bug: Core should fault on misaligned branch source instruction, not on the target.

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

Apache License 2.0

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Bug: Core should fault on misaligned branch source instruction, not on the target. #2

Closed ultraembedded closed 4 years ago

ultraembedded commented 4 years ago

In v2.1 of the base ISA spec;

"An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not four-byte aligned. This exception is reported on the branch or jump instruction, not on the target instruction."