ultraembedded / biriscv

32-bit Superscalar RISC-V CPU
Apache License 2.0
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Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH #24

Open Gianluke27 opened 11 months ago

Gianluke27 commented 11 months ago

According to the "ricv_privileged_spec" document on page 8 the instructions 0xC00, 0xC01 and 0xC80 refer to user-side instructions, while the machine-side instructions, i.e. mcycle, mtime and mcycleh are described on page 11 with the following opcodes: 0xB00, 0XB01, 0xB80.

In biriscv_defs on line 350 there are definitions to be modified.