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ultraembedded / biriscv

32-bit Superscalar RISC-V CPU
Apache License 2.0
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TCL file for FPGA build #8

Open alaasal opened 3 years ago

alaasal commented 3 years ago

Hello,

You have done great work! Could you please share with us the TCL script used/generated from the FPGA run? And maybe more details on building the image and FPGA run flow?

Thanks a lot, Alaa

emiliofmc7 commented 3 years ago

Hello, Has the FPGA been able to run?, second, how have you loaded initialized memory from verilog file?

Thanks, Emilio

Hello,

You have done great work! Could you please share with us the TCL script used/generated from the FPGA run? And maybe more details on building the image and FPGA run flow?

Thanks a lot, Alaa