The instruction replay behavior has changed in Maxwell compared to
earlier designs, and is now handled by the individual units, not the
scheduler 1. As such, for compute capabilities 5 and later, we need
to update the memory model to handle this properly; otherwise, we end up
with a pressure on issue that is way too high compared to the reality.
Elarnon
commented
4 years ago
The instruction replay behavior has changed in Maxwell compared to earlier designs, and is now handled by the individual units, not the scheduler 1. As such, for compute capabilities 5 and later, we need to update the memory model to handle this properly; otherwise, we end up with a pressure on
issuethat is way too high compared to the reality.